-- GOP_XCR3064XL 20pin template; delete this line -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: -- Design Name: -- Component Name: -- Target Device: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- -- Additional Comments: -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity ucf_xcr3064xl_20 is Port ( osc,clk0,clk1 : in std_logic ; rcout : in std_logic ; tp2,tp3,tp4,tp5,tp6: inout std_logic ; ptck,ptms,ptdi,ptdo: inout std_logic ; pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8,pin9: inout std_logic ; pin11,pin12,pin13,pin14,pin15,pin16,pin17,pin18,pin19: inout std_logic ; rcin : out std_logic); end ucf_xcr3064xl_20 ; architecture Behavioral of ucf_xcr3064xl_20 is begin end Behavioral;