set import_dir "C:/Mchpprj/FPGA_MiV_sources"

set project_folder_name RV32IMC_BaseDesign
set Libero_project_name RV32IMC_BaseDesign
set project_dir "./$project_folder_name"

set toplevel {TOP}
set currdate "_15mar21_1930"

set prog_filename RV32IMA_L1_AHB_$toplevel$currdate

puts "-------------------------------------------------------------------------"
puts "-----------------------CREATING NEW PROJECT------------------------------"
puts "-------------------------------------------------------------------------"

new_project -location ${project_dir} -name ${Libero_project_name} -project_description {test design ${currdate} } -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 \
-ondemand_build_dh 1 -use_relative_path 0 -linked_files_root_dir_env {} -hdl {VHDL} -family {SmartFusion2} -die {M2S010} -package {400 VF} -speed {STD} \
-die_voltage {1.2} -part_range {COM} -adv_options {DSW_VCCA_VOLTAGE_RAMP_RATE:100_MS} -adv_options {IO_DEFT_STD:LVCMOS 3.3V} \
-adv_options {PLL_SUPPLY:PLL_SUPPLY_33} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} \
-adv_options {TEMPR:COM} -adv_options {VCCI_1.2_VOLTR:COM} -adv_options {VCCI_1.5_VOLTR:COM} -adv_options {VCCI_1.8_VOLTR:COM} -adv_options {VCCI_2.5_VOLTR:COM} \
-adv_options {VCCI_3.3_VOLTR:COM} -adv_options {VOLTR:COM} 

puts "-------------------------------------------------------------------------"
puts "-----------------------IMPORTING COMPONENTS------------------------------"
puts "-------------------------------------------------------------------------"

source ${import_dir}/components/COREAHBLSRAM_C0.tcl 
source ${import_dir}/components/COREJTAGDEBUG_C0.tcl 
source ${import_dir}/components/CoreGPIO_C0.tcl 
source ${import_dir}/components/MIV_RV32IMC_C0.tcl 
source ${import_dir}/components/OSC_C0.tcl 
source ${import_dir}/components/TOP.tcl 

set_root $toplevel
build_design_hierarchy
save_project 


puts "-------------------------------------------------------------------------"
puts "--------------------APPLYING DESIGN CONSTRAINTS--------------------------"
puts "-------------------------------------------------------------------------"

import_files \
         -convert_EDN_to_HDL 0 \
         -io_pdc ${import_dir}/constraint/io/SMF2000_IO.pdc

import_files \
         -convert_EDN_to_HDL 0 \
         -library {work} \
         -sdc ${import_dir}/constraint/async_groups.sdc \
         -sdc ${import_dir}/constraint/jtag_tck_constraint.sdc 

# Associate SDC constraint file to Place and Route tool
#organize_tool_files -tool {PLACEROUTE} \
#    -file $project_dir/constraint/io/SMF2000_IO.pdc \
#    -module $toplevel -input_type {constraint}

run_tool -name {CONSTRAINT_MANAGEMENT}
derive_constraints_sdc 
run_tool -name {GENERATE_MEMORY_MAP} 
save_project 

puts "-------------------------------------------------------------------------"
puts "------------------------ ORGANIZE CONSTRAINTS ---------------------------"
puts "-------------------------------------------------------------------------"

organize_tool_files -tool {SYNTHESIZE} \
         -file ${project_dir}/constraint/${toplevel}_derived_constraints.sdc \
         -file ${project_dir}/constraint/jtag_tck_constraint.sdc \
         -module ${toplevel} -input_type {constraint} 

organize_tool_files -tool {PLACEROUTE} \
         -file ${project_dir}/constraint/io/SMF2000_IO.pdc \
         -file ${project_dir}/constraint/${toplevel}_derived_constraints.sdc \
         -file ${project_dir}/constraint/jtag_tck_constraint.sdc \
         -module ${toplevel} -input_type {constraint} 

organize_tool_files -tool {VERIFYTIMING} \
         -file ${project_dir}/constraint/${toplevel}_derived_constraints.sdc \
         -file ${project_dir}/constraint/jtag_tck_constraint.sdc \
         -file ${project_dir}/constraint/async_groups.sdc \
         -module ${toplevel} -input_type {constraint} 

save_project 

puts "-------------------------------------------------------------------------"
puts "----------------------PROJECT CREATION COMPLETED-------------------------"
puts "-------------------------------------------------------------------------"

puts "-------------------------------------------------------------------------"
puts "-----------------------------SYNTHESIS-----------------------------------"
puts "-------------------------------------------------------------------------"
configure_tool -name {SYNTHESIZE} -params {BLOCK_MODE:false} -params {BLOCK_PLACEMENT_CONFLICTS:ERROR} -params {BLOCK_ROUTING_CONFLICTS:LOCK} -params {CLOCK_ASYNC:12} -params {CLOCK_DATA:5000} -params {CLOCK_GLOBAL:2} -params {PA4_GB_COUNT:8} -params {PA4_GB_MAX_RCLKINT_INSERTION:16} -params {PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT:300} -params {RAM_OPTIMIZED_FOR_POWER:0} -params {RETIMING:false} -params {SYNPLIFY_OPTIONS:} -params {SYNPLIFY_TCL_FILE:} 
run_tool -name {SYNTHESIZE} 

puts "-------------------------------------------------------------------------"
puts "--------------------------PLACE AND ROUTE--------------------------------"
puts "-------------------------------------------------------------------------"
configure_tool -name {PLACEROUTE} -params {DELAY_ANALYSIS:MAX} -params {EFFORT_LEVEL:false} -params {INCRPLACEANDROUTE:false} -params {IOREG_COMBINING:true} -params {MULTI_PASS_CRITERIA:VIOLATIONS} -params {MULTI_PASS_LAYOUT:false} -params {NUM_MULTI_PASSES:5} -params {PDPR:false} -params {RANDOM_SEED:0} -params {REPAIR_MIN_DELAY:true} -params {SLACK_CRITERIA:WORST_SLACK} -params {SPECIFIC_CLOCK:} -params {START_SEED_INDEX:1} -params {STOP_ON_FIRST_PASS:false} -params {TDPR:true} 
run_tool -name {PLACEROUTE} 

puts "-------------------------------------------------------------------------"
puts "--------------------------TIMING ANALYSIS--------------------------------"
puts "-------------------------------------------------------------------------"
configure_tool -name {VERIFYTIMING} -params {CONSTRAINTS_COVERAGE:1} -params {FORMAT:XML} -params {MAX_EXPANDED_PATHS_TIMING:1} -params {MAX_EXPANDED_PATHS_VIOLATION:0} -params {MAX_PARALLEL_PATHS_TIMING:1} -params {MAX_PARALLEL_PATHS_VIOLATION:1} -params {MAX_PATHS_INTERACTIVE_REPORT:1000} -params {MAX_PATHS_TIMING:5} -params {MAX_PATHS_VIOLATION:20} -params {MAX_TIMING_FAST_HV_LT:1} -params {MAX_TIMING_MULTI_CORNER:1} -params {MAX_TIMING_SLOW_LV_HT:1} -params {MAX_TIMING_VIOLATIONS_FAST_HV_LT:1} -params {MAX_TIMING_VIOLATIONS_MULTI_CORNER:1} -params {MAX_TIMING_VIOLATIONS_SLOW_LV_HT:1} -params {MIN_TIMING_FAST_HV_LT:1} -params {MIN_TIMING_MULTI_CORNER:1} -params {MIN_TIMING_SLOW_LV_HT:1} -params {MIN_TIMING_VIOLATIONS_FAST_HV_LT:1} -params {MIN_TIMING_VIOLATIONS_MULTI_CORNER:1} -params {MIN_TIMING_VIOLATIONS_SLOW_LV_HT:1} -params {SLACK_THRESHOLD_VIOLATION:0.0} -params {SMART_INTERACTIVE:true} 
run_tool -name {VERIFYTIMING} 

puts "-------------------------------------------------------------------------"
puts "--------------------GENERATING PROGRAMMING FILES-------------------------"
puts "-------------------------------------------------------------------------"
run_tool -name {GENERATEPROGRAMMINGDATA} 
run_tool -name {GENERATEPROGRAMMINGFILE} 

puts "-------------------------------------------------------------------------"
puts "----------------------EXPORT PROGRAMMING FILES---------------------------"
puts "-------------------------------------------------------------------------"
export_pin_reports \
         -export_dir ${project_dir}/designer/${toplevel}/export \
         -pin_report_by_name 1 \
         -pin_report_by_pkg_pin 1 \
         -bank_report 1 \
         -io_report 1 
export_prog_job \
         -job_file_name ${prog_filename} \
         -export_dir ${project_dir}/designer/${toplevel}/export \
         -bitstream_file_type {TRUSTED_FACILITY} \
         -bitstream_file_components {FABRIC} \
         -include_plaintext_passkey 0 \
         -design_bitstream_format {STP} \
         -prog_optional_procedures {} \
         -sanitize_envm 0 
export_bitstream_file \
         -file_name ${prog_filename} \
         -export_dir ${project_dir}/designer/${toplevel}/export \
         -format {STP PPD} \
         -for_ihp 0 \
         -limit_SVF_file_size 0 \
         -limit_SVF_file_by_max_filesize_or_vectors {} \
         -svf_max_filesize {} \
         -svf_max_vectors {} \
         -master_file 0 \
         -master_file_components {} \
         -encrypted_uek1_file 0 \
         -encrypted_uek1_file_components {} \
         -encrypted_uek2_file 0 \
         -encrypted_uek2_file_components {} \
         -trusted_facility_file 1 \
         -trusted_facility_file_components {FABRIC} \
         -add_golden_image 0 \
         -golden_image_address {} \
         -golden_image_design_version {} \
         -add_update_image 0 \
         -update_image_address {} \
         -update_image_design_version {} \
         -serialization_stapl_type {SINGLE} \
         -serialization_target_solution {FLASHPRO_3_4_5} \
         -master_include_plaintext_passkey 0 \
         -uek1_include_plaintext_passkey 0 \
         -uek2_include_plaintext_passkey 0 \
         -sanitize_envm 0 
export_smart_debug_data \
         -file_name ${prog_filename} \
         -export_dir ${project_dir}/designer/${toplevel}/export \
         -probes 1 \
         -package_pins 0 \
         -memory_blocks 1 \
         -security_data 1 \
         -security_data 0 \
         -chain 1 \
         -programmer_settings 1 \
         -ios_states 1 \
         -generate_bitstream 0 \
         -bitstream_format {PPD} \
         -bitstream_security 0 \
         -bitstream_fabric 0 \
         -bitstream_envm 0 \
         -master_include_plaintext_passkey 0 

puts "-------------------------------------------------------------------------"
puts "--------------------- PLEASE Using FIRMWARE CATALOG----------------------"
puts "------------------------EXPORT FIRMWARE FILES----------------------------"
puts "-------------------------------------------------------------------------"
#export_firmware -export_dir ${project_dir} -create_project 0 -software_ide {SoftConsole} 
         
save_project


