# Exporting core COREJTAGDEBUG_C0 to TCL
# Exporting Create design command for core COREJTAGDEBUG_C0
create_and_configure_core -core_vlnv {Actel:DirectCore:COREJTAGDEBUG:3.1.100} -component_name {COREJTAGDEBUG_C0} -params {\
"IR_CODE_TGT_0:0x55"  \
"IR_CODE_TGT_1:0x56"  \
"IR_CODE_TGT_2:0x57"  \
"IR_CODE_TGT_3:0x58"  \
"IR_CODE_TGT_4:0x59"  \
"IR_CODE_TGT_5:0x5a"  \
"IR_CODE_TGT_6:0x5b"  \
"IR_CODE_TGT_7:0x5c"  \
"IR_CODE_TGT_8:0x5d"  \
"IR_CODE_TGT_9:0x5e"  \
"IR_CODE_TGT_10:0x5f"  \
"IR_CODE_TGT_11:0x60"  \
"IR_CODE_TGT_12:0x61"  \
"IR_CODE_TGT_13:0x62"  \
"IR_CODE_TGT_14:0x63"  \
"IR_CODE_TGT_15:0x64"  \
"NUM_DEBUG_TGTS:1"  \
"TGT_ACTIVE_HIGH_RESET_0:true"  \
"TGT_ACTIVE_HIGH_RESET_1:true"  \
"TGT_ACTIVE_HIGH_RESET_2:true"  \
"TGT_ACTIVE_HIGH_RESET_3:true"  \
"TGT_ACTIVE_HIGH_RESET_4:true"  \
"TGT_ACTIVE_HIGH_RESET_5:true"  \
"TGT_ACTIVE_HIGH_RESET_6:true"  \
"TGT_ACTIVE_HIGH_RESET_7:true"  \
"TGT_ACTIVE_HIGH_RESET_8:true"  \
"TGT_ACTIVE_HIGH_RESET_9:true"  \
"TGT_ACTIVE_HIGH_RESET_10:true"  \
"TGT_ACTIVE_HIGH_RESET_11:true"  \
"TGT_ACTIVE_HIGH_RESET_12:true"  \
"TGT_ACTIVE_HIGH_RESET_13:true"  \
"TGT_ACTIVE_HIGH_RESET_14:true"  \
"TGT_ACTIVE_HIGH_RESET_15:true"  \
"UJTAG_BYPASS:false"   }
# Exporting core COREJTAGDEBUG_C0 to TCL done
