This design is targeted for xczu2cg board (part number: xczu2cg-sbva484-1-e)

Zynq UltraScale+ Design Summary

Device	xczu2cg
SpeedGrade	-1
Part	xczu2cg-sbva484-1-e
Description	Zynq UltraScale+ PS Configuration Report
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction	Drive Strength(mA)
MIO 0	Quad SPI Flash	sclk_out	schmitt	slow	pullup	out	12
MIO 1	Quad SPI Flash	miso_mo1	schmitt	slow	pullup	inout	12
MIO 2	Quad SPI Flash	mo2	schmitt	slow	pullup	inout	12
MIO 3	Quad SPI Flash	mo3	schmitt	slow	pullup	inout	12
MIO 4	Quad SPI Flash	mosi_mi0	schmitt	slow	pullup	inout	12
MIO 5	Quad SPI Flash	n_ss_out	schmitt	slow	pullup	out	12
MIO 6	Feedback Clk	clk_for_lpbk	schmitt	slow	pullup	out	12
MIO 7	GPIO0 MIO	gpio0[7]	schmitt	slow	pullup	inout	12
MIO 8	I2C 1	scl_out	schmitt	slow	pullup	inout	12
MIO 9	I2C 1	sda_out	schmitt	slow	pullup	inout	12
MIO 10	UART 0	rxd	schmitt	slow	pullup	in	12
MIO 11	UART 0	txd	schmitt	slow	pullup	out	12
MIO 12	GPIO0 MIO	gpio0[12]	schmitt	slow	pullup	inout	12
MIO 13	SD 0	sdio0_data_out[0]	cmos	slow	disable	inout	12
MIO 14	SD 0	sdio0_data_out[1]	cmos	slow	disable	inout	12
MIO 15	SD 0	sdio0_data_out[2]	cmos	slow	disable	inout	12
MIO 16	SD 0	sdio0_data_out[3]	cmos	slow	disable	inout	12
MIO 17	GPIO0 MIO	gpio0[17]	schmitt	slow	pullup	inout	12
MIO 18	I2C 0	scl_out	schmitt	slow	pullup	inout	12
MIO 19	I2C 0	sda_out	schmitt	slow	pullup	inout	12
MIO 20	GPIO0 MIO	gpio0[20]	schmitt	slow	pullup	inout	12
MIO 21	SD 0	sdio0_cmd_out	cmos	slow	disable	inout	12
MIO 22	SD 0	sdio0_clk_out	schmitt	slow	disable	out	12
MIO 23	GPIO0 MIO	gpio0[23]	schmitt	slow	pullup	inout	12
MIO 24	SD 0	sdio0_cd_n	cmos	slow	disable	in	12
MIO 25	GPIO0 MIO	gpio0[25]	schmitt	slow	pullup	inout	12
MIO 26	GPIO1 MIO	gpio1[26]	schmitt	slow	pullup	inout	12
MIO 27	DPAUX	dp_aux_data_out	schmitt	slow	pullup	out	12
MIO 28	DPAUX	dp_hot_plug_detect	schmitt	slow	pullup	in	12
MIO 29	DPAUX	dp_aux_data_oe	schmitt	slow	pullup	out	12
MIO 30	DPAUX	dp_aux_data_in	schmitt	slow	pullup	in	12
MIO 31	PCIE	reset_n	schmitt	slow	pullup	out	12
MIO 32	GPIO1 MIO	gpio1[32]	schmitt	slow	pullup	inout	12
MIO 33	GPIO1 MIO	gpio1[33]	schmitt	slow	pullup	inout	12
MIO 34	GPIO1 MIO	gpio1[34]	schmitt	slow	pullup	inout	12
MIO 35	GPIO1 MIO	gpio1[35]	schmitt	slow	pullup	inout	12
MIO 36	GPIO1 MIO	gpio1[36]	schmitt	slow	pullup	inout	12
MIO 37	GPIO1 MIO	gpio1[37]	schmitt	slow	pullup	inout	12
MIO 38	GPIO1 MIO	gpio1[38]	schmitt	slow	pullup	inout	12
MIO 39	GPIO1 MIO	gpio1[39]	schmitt	slow	pullup	inout	12
MIO 40	GPIO1 MIO	gpio1[40]	schmitt	slow	pullup	inout	12
MIO 41	GPIO1 MIO	gpio1[41]	schmitt	slow	pullup	inout	12
MIO 42	GPIO1 MIO	gpio1[42]	schmitt	slow	pullup	inout	12
MIO 43	GPIO1 MIO	gpio1[43]	schmitt	slow	pullup	inout	12
MIO 44	GPIO1 MIO	gpio1[44]	schmitt	slow	pullup	inout	12
MIO 45	GPIO1 MIO	gpio1[45]	schmitt	slow	pullup	inout	12
MIO 46	GPIO1 MIO	gpio1[46]	schmitt	slow	pullup	inout	12
MIO 47	GPIO1 MIO	gpio1[47]	schmitt	slow	pullup	inout	12
MIO 48	GPIO1 MIO	gpio1[48]	schmitt	slow	pullup	inout	12
MIO 49	GPIO1 MIO	gpio1[49]	schmitt	slow	pullup	inout	12
MIO 50	GPIO1 MIO	gpio1[50]	schmitt	slow	pullup	inout	12
MIO 51	GPIO1 MIO	gpio1[51]	schmitt	slow	pullup	inout	12
MIO 52	USB 0	ulpi_clk_in	schmitt	slow	pullup	in	12
MIO 53	USB 0	ulpi_dir	schmitt	slow	pullup	in	12
MIO 54	USB 0	ulpi_tx_data[2]	schmitt	slow	pullup	inout	12
MIO 55	USB 0	ulpi_nxt	schmitt	slow	pullup	in	12
MIO 56	USB 0	ulpi_tx_data[0]	schmitt	slow	pullup	inout	12
MIO 57	USB 0	ulpi_tx_data[1]	schmitt	slow	pullup	inout	12
MIO 58	USB 0	ulpi_stp	schmitt	slow	pullup	out	12
MIO 59	USB 0	ulpi_tx_data[3]	schmitt	slow	pullup	inout	12
MIO 60	USB 0	ulpi_tx_data[4]	schmitt	slow	pullup	inout	12
MIO 61	USB 0	ulpi_tx_data[5]	schmitt	slow	pullup	inout	12
MIO 62	USB 0	ulpi_tx_data[6]	schmitt	slow	pullup	inout	12
MIO 63	USB 0	ulpi_tx_data[7]	schmitt	slow	pullup	inout	12
MIO 64	Gem 3	rgmii_tx_clk	schmitt	slow	pullup	out	12
MIO 65	Gem 3	rgmii_txd[0]	schmitt	slow	pullup	out	12
MIO 66	Gem 3	rgmii_txd[1]	schmitt	slow	pullup	out	12
MIO 67	Gem 3	rgmii_txd[2]	schmitt	slow	pullup	out	12
MIO 68	Gem 3	rgmii_txd[3]	schmitt	slow	pullup	out	12
MIO 69	Gem 3	rgmii_tx_ctl	schmitt	slow	pullup	out	12
MIO 70	Gem 3	rgmii_rx_clk	schmitt	slow	pullup	in	12
MIO 71	Gem 3	rgmii_rxd[0]	schmitt	slow	pullup	in	12
MIO 72	Gem 3	rgmii_rxd[1]	schmitt	slow	pullup	in	12
MIO 73	Gem 3	rgmii_rxd[2]	schmitt	slow	pullup	in	12
MIO 74	Gem 3	rgmii_rxd[3]	schmitt	slow	pullup	in	12
MIO 75	Gem 3	rgmii_rx_ctl	schmitt	slow	pullup	in	12
MIO 76	MDIO 3	gem3_mdc	schmitt	slow	pullup	out	12
MIO 77	MDIO 3	gem3_mdio_out	schmitt	slow	pullup	inout	12

PS Clocks information

PSS REF CLK : 33.333

Name	Source	Input Frequency (MHz)
APLL	PSS_REF_CLK	2400.000
DPLL	PSS_REF_CLK	2800.000
VPLL	PSS_REF_CLK	3000.000
RPLL	PSS_REF_CLK	1500.000
IOPLL	PSS_REF_CLK	3000.000

Peripheral	Requested Frequency (MHz)	Source	Actual Frequency (MHz)
GEM3 freq (MHz)	125	IOPLL	125.000000
USB0 freq (MHz)	250	IOPLL	250.000000
QSPI freq (MHz)	300	IOPLL	300.000000
SDIO0 freq (MHz)	200	IOPLL	187.500000
UART0 freq (MHz)	100	IOPLL	100.000000
I2C0 freq (MHz)	100	IOPLL	100.000000
I2C1 freq (MHz)	100	IOPLL	100.000000
CPU_R5 freq (MHz)	500	IOPLL	500.000000
IOU_SWITCH freq (MHz)	267	IOPLL	250.000000
LPD_SWITCH freq (MHz)	500	IOPLL	500.000000
LPD_LSBUS freq (MHz)	100	IOPLL	100.000000
GEM_TSU freq (MHz)	250	IOPLL	250.000000
TIMESTAMP freq (MHz)	100	PSS_REF_CLK	33.333332
PSU__CRL_APB__USB3_REF_CTRL__freqmhz	20	IOPLL	20.000000
PCAP freq (MHz)	200	IOPLL	187.500000
DBG_LPD freq (MHz)	250	IOPLL	250.000000
ADMA freq (MHz)	500	IOPLL	500.000000
PL0 freq (MHz)	100	IOPLL	100.000000
PL1 freq (MHz)	65	IOPLL	62.500000
AMS freq (MHz)	50	IOPLL	50.000000
ACPU freq (MHz)	1200	APLL	1200.000000
DBG FPD freq (MHz)	250	IOPLL	250.000000
DP VIDEO freq (MHz)	300	VPLL	300.000000
DP AUDIO freq (MHz)	25	RPLL	25.000000
DP STC freq (MHz)	27	RPLL	26.785715
PCIE freq (MHz)	250	IOPLL	250.000000
DDR_CTRL freq MHz)	175.000	DPLL	175.000000
GDMA freq (MHz)	600	APLL	600.000000
DPDMA freq (MHz)	600	APLL	600.000000
TOPSW_MAIN freq (MHz)	533.333	APLL	400.000000
TOPSW_LSBUS freq (MHz)	100	IOPLL	100.000000
DBG TSTMP freq (MHz)	250	IOPLL	250.000000

DDR Memory information

Parameter name	Value	Description
ENABLE	1	Enable the PS DDR Controller
DDR Interface freq (MHz)	350	--
MEMORY TYPE	LPDDR 4	Type of memory interface
DM DBI	Components
BUS WIDTH	32 Bit	Data width of DDR interface, not including ECC data width
ECC	Disabled	Enables error correction code support
SPEED BIN	LPDDR4_1066	Speed Bin
CL	NA	Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL	NA	CAS write latency setting in memory clock cycles
DDR AL	0	Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD	18	tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP	12	Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC	63	Row cycle time (ns)
T RAS MIN	42	Minimum number of memory clock cycles required between an Active and Precharge command
T FAW	40.0	Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH	32 Bits	Width of individual DRAM components
DEVICE CAPACITY	8192 MBits	Storage capacity of individual DRAM components
BG ADDR COUNT	NA	Number of bank group address pins
RANK ADDR COUNT	0	Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT	3	Number of bank address pins
ROW ADDR COUNT	15	Number of row address pins
COL ADDR COUNT	10	Number of column address bits
C_DDR_RAM_HIGHADDR	0x3FFFFFFF	--

GT lanes information

Protocol	GT lane#	Ref Clk Sel	Ref freq (MHz)
PCIe	GT Lane0	Ref Clk0	100
USB0	GT Lane1	Ref Clk0	100
DP	GT Lane2	Ref Clk2	27