Project Settings
Project Name top_syn Implementation Name synthesis
Top Module work.top Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 659 10228 0 - 00m:07s - 04.06.2018
13:59:20
(premap)Complete 117 24 0 0m:02s 0m:02s 189MB 04.06.2018
13:59:26
(fpga_mapper)Complete 185 80 0 0m:10s 0m:10s 198MB 04.06.2018
13:59:37
Multi-srs Generator Complete00m:01s04.06.2018
13:59:22

Area Summary
Carry Cells 269 Sequential Cells 2353
DSP Blocks (MACC) (dsp_used) 0 I/O Cells 67
Global Clock Buffers 3 RAM64x18 (v_ram) 6
LUTs (total_luts) 2392

Timing Summary
Clock NameReq FreqEst FreqSlack
top_sb_CCC_0_FCCC|GL2_net_inferred_clock100.0 MHz97.5 MHz-0.253
System100.0 MHzNANA

Optimizations Summary
Combined Clock Conversion 0 / 1