FPGA & Adaptive SoC Design: Integrate Functions Systematically
Plan processing, programmable logic, memory, NoC and external interfaces as one system architecture and integrate them step by step.
Designing with an Adaptive SoC involves more than implementing individual FPGA functions. Data has to move between the processing system, programmable logic, memory and external interfaces, while clocking, pinout and high-speed I/O must match the final hardware.
The central design question therefore becomes: which function belongs where, and how should the individual domains be connected into a reproducible system?
Practical example: from functional blocks to an integrated Adaptive SoC system
The following example illustrates one possible development workflow using AMD Versal AI Edge Gen 2.
TE0960 can first be used as an evaluation platform. TE0965 then provides the same technology generation as a System-on-Module for integration into application-specific hardware.
Partition functions between processing and PL
The first step is functional partitioning.
Time-critical and highly parallel tasks can be implemented in programmable logic, while software running on the processing system can handle configuration, control, communication and functions that change more frequently during operation.
The important factor is not only the computing capability of each domain, but also the data movement between them. This partitioning should therefore be defined early in the FPGA and Adaptive SoC design.
Include memory and NoC in the data path
As soon as data moves between several processing domains, memory architecture and the NoC become part of the functional design.
TE0960 combines AMD Versal AI Edge Gen 2 with three 32-bit LPDDR5 memory areas, providing a platform for developing and evaluating such system architectures.
Instead of adding memory after the functional blocks are complete, bandwidth, data paths and memory access should be considered while the architecture is being developed. This makes it possible to determine early which data can be processed directly and which data needs to move through memory or other parts of the system.
Integrate I/O and high-speed interfaces early
A working FPGA design alone does not yet form a complete system.
External sensors, converters, communication interfaces and other devices determine which I/O resources, transceivers and clocks are required.
TE0965 provides extensive resources for this purpose, including 20 GTYP transceivers on the PL side, additional GTYP and PS-GTR transceivers, as well as X5IO, HDIO and MIO resources These resources have to be planned together with pinout, clocking and the carrier architecture.
Transfer the validated architecture to the target hardware
Once processing, PL, memory and I/O have been developed as one system, the architecture can be transferred to application-specific hardware.
This is where evaluation and integration differ. TE0960 can be used to explore functions and data paths first. For the target system, TE0965 combines AMD Versal AI Edge Gen 2 with four 32-bit LPDDR5 memory areas, QSPI Flash, Ethernet and USB PHYs and clocking on a 75 × 90 mm SoM.
Why system architecture matters in practice
Integration issues in FPGA and Adaptive SoC projects often occur not inside an individual functional block, but at the boundaries between blocks.
A logic function may operate correctly on its own and still cause problems at system level if memory access, data bandwidth, clock domains or external interfaces do not match the architecture.
The practical approach is therefore to develop processing, PL, NoC, memory and I/O as one connected data path rather than treating them as isolated tasks.
Fundamental architecture decisions can first be evaluated on the development platform.
For the final product, the computing platform can then be consolidated on a SoM while the carrier provides the application-specific interfaces.
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