PCIe FMC Carrier with AMD Virtex-7 FPGA, 8 Lane PCIe GEN2, SODIMM SDRAM

US$3,283.21

Ready to ship today, Delivery time appr. 1-3 workdays

Article number: TEC0330-05

Article status: EOL

Stock: 4

Product information "PCIe FMC Carrier with AMD Virtex-7 FPGA, 8 Lane PCIe GEN2, SODIMM SDRAM"

This product is offered at a discount and is valid while stocks last!
____________________________________________________

The predecessor of this article is TEC0330-04. All changes are in the Product Change Notification (PCN).

Note: Carrier without pads for conduction cooling!

The Trenz Electronic TEC0330 is a PCI Express form factor card (PCIe 2.0 or higher) integrating the AMD Virtex-7 XC7VX330T FPGA chip. This high-end FPGA card is designed for maximum system performance and intended for use in applications with high demands on system throughput. There is a SO-DIMM socket on the board for standard DDR3 SDRAM extension memory module.

The TEC0330 features HPC (High Pin Count) ANSI/VITA 57.1 compatible FMC interface connector for standard I/O Mezzanine modules. Other interface connectors found on-board include JTAG for accessing FPGA and on-board System Controller CPLD, and also connector with 5 high-speed I/O differential signaling pairs.

The TEC0330 FPGA board is intended to be used as add-on card in a PCIe 2.0 or higher capable host systems, it can not be used as a stand-alone device.

Key Features

AMD Virtex-7 FPGA module XC7VX330T-2FFG1157C (commercial temperature range)
PCI Express 2.0 x8 card with maximum throughput of 4 GB/s
FMC High Pin Count (HPC) connector
8 FPGA MGT lanes available on PCIe interface
DDR3 SODIMM SDRAM socket
256-Mbit (32-MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
- FPGA
- JTAG port (SPI indirect, bus width x4)
External clock input via SMA coaxial connector
28 GTH transceivers, each with up to 13.1 Gbit/s data transmission rate
FPGA configuration through:
- JTAG connector
- SPI Flash memory
Programmable quad clock generator
TI LMK04828B ultra low-noise JESD204B compliant clock jitter cleaner
On-board high-efficiency DC-DC converters
Up to 202 FPGA I/O pins available on FMC connector (up to 101 LVDS pairs possible)
System management and power sequencing
AES bit-stream encryption
eFUSE bit-stream encryption

Other assembly options for cost or performance optimization plus high volume prices available on request.

Development Support

Latest documentation, design support files and reference designs with source files are available for download free of charge.

Scope of Delivery

1 x TEC0330-05 Trenz Electronic PCIe FMC Carrier with AMD Virtex-7 330T FPGA

Additional Information

Manufacturer's article number: TEC0330-05
Trenz Electronic TEC0330 Wiki
Support Forum

All modules produced by Trenz Electronic are developed and manufactured in Germany.

Properties "PCIe FMC Carrier with AMD Virtex-7 FPGA, 8 Lane PCIe GEN2, SODIMM SDRAM"

Properties

FPGA Manufacturer:	AMD
FPGA/SoC Architecture:	7 Series
FPGA/SoC Family:	Virtex
FPGA/SoC Type:	FPGA

Data according to manufacturer. Errors and changes reserved.

Downloads

File	File-Extension	Description
Bit-File	*.bit	FPGA Configuration File
Diverse Reports	--	Report files in different formats

Component	Description
IP-Interfaces	I2C, ASIO (AXI-Stream to IO), SPI-Flash, Uart

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	I2C,SPI-Flash,UART
TE-IP	ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO
TE-IP	Startupe2,LabTools Frequency Counter

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Xilinx-IP	VIO (Virtual Input/Output)
TE-IP	Labtools Frequency Counter, Startupe2 Primitive Wrapper

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
Reference Design	Reference Designs sort by ISE/EDK Version
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Component	Description
Interface IPs	DDR3, GPIO, Uart0, QSPI and Ethernet

Application	Description
hello_world	Xilinx Hello World Example (.elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	MicroBlaze, MB-Debug, Uartlite, MIG7 for DDR3, QSPI, Timer, Ethernet Lite
TE-IP	ASIO GPIO (AXI-Stream to GPIO)

Application	Description
Hello World	Xilinx Hello world ( generate elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO,ILA
TE-IP	unio_mac

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Interface IPs	QSPI, Uart, ASIO (Axi-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	ILA, VIO, CLK-Wizard
TE-IP	F32C, Vector_LED, UART_MON

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Component	Description
IP-Interfaces	DDR3, QSPI, Uart, I2C, Ethernet, ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite, VIO
TE-IP	ASIO (AXI-Stream to IO), labtools_fmeter

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
te_spi_bootloader	SPI Bootloader (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
memory_tests	Xilinx Memory Example (.elf only)

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Component	Description
Zynq Processor	activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C,2x SD,1x Ethernet

Application	Description
zynq_fsbl	Zynq First Stage Bootloader (for hdmi modified and provided as library in /sw_lib/)
hello_world	Xilinx Hello World Example

Digilent
OHO-Elektronik
Sundance
Trenz_Electronic - Documents and Design files for Trenz Electronic Products
inrevium
reference
Files SBSE____.ZZC
Size 4 B / Modified 29.09.2026 - 16:31:35

TEC0330 PCIe Carrier with Xilinx Virtex-7 and a FMC connector

TEC0330 PCIe FMC Carrier - Wiki with TRM, reference projects, application notes and more
- TEC0330 TRM - Technical Reference Manual
- TEC0330 Reference Designs - Reference Design Description for Vivado 2017.2 and newer
- TEC0330 CPLD Firmware - Firmware Description
- TEC0330 Product Change Notifications - PCN (see also Schematic Change History and TRM)

Links

Shop TEC0330 - contains prices, available stock, disposability, scope of delivery and more
Download area - various reference designs, schematics, hardware designs and more
TE0790 Resources - XMOD JTAG Programmer documentation
Pinout/Tracelength Table - illustration of pinout, tracelength and cross reference Information of modules with different baseboards

Support

For support, please go to http://forum.trenz-electronic.de/ or contact support@trenz-electronic.de

Name	Folder	Description
Source Name	<design_name><folder>	Source Description
PetaLinux Project	<design_name>/os/petalinux	PetaLinux Project with Ethernet,USB,RTC

PCIe FMC Carrier with AMD Virtex-7 FPGA, 8 Lane PCIe GEN2, SODIMM SDRAM

Product information "PCIe FMC Carrier with AMD Virtex-7 FPGA, 8 Lane PCIe GEN2, SODIMM SDRAM"

Key Features

Development Support

Scope of Delivery

Additional Information

Downloads

TEC0850 Basic Design

CR00100 Basic Example

CR00100 Basic Example

CR00103 Hyperram Citrobits

CR00103 Certus Test

CR00107 Basic Hello World Example

TE0802 Basic Linux Example

TE0802 Basic Linux Example

TE0802 Basic Linux Example

TE0802 Basic Linux Example

TE0950 Vitis AI Reference Design

TE0950 Basic Linux Example

TE0950 Basic Linux Example

TEI0022 Basic Example

TEI0022 Basic Example

TE0717 Hello World Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0003 LED Sequencer Example

TEI0003 NIOS SDRAM Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0010 Basic Example

TEI0010 Basic Example

TEI0010 Basic Example

TEI0010 Basic Example

TEM0001 Test Board Example

TEI0050 Basic Example

TEI0050 Basic Example

TEI0050 Basic Example

TEI0015 DAQ Capture Demo

TEI0015 Data Capture Demo

TEI0015 Jupyter Demo

TEI0016 DAQ Capture Demo

TEI0016 Data Capture Demo

TEI0016 Jupyter Demo

TEI0023 DAQ Capture Demo

TEI0023 Data Capture Demo

TEI0023 Jupyter Demo

TE0890 Hello World Example

TE0890 Hello World Example

ZynqberryZero Demo VIDEO/AUDIO Design with RPI video camera stream to monitor

Basic Linux Example

ZynqberryZero Demo VIDEO/AUDIO Design with RPI video camera stream to monitor

ZynqberryZero Demo VIDEO/AUDIO Design with RPI video camera stream to monitor

TEM0005 Webserver Demo1

MicroBlaze Basic-System

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 Basic Example

TE0725LP Frequency Measurement

TE0725LP Basic Example

TE0725LP Basic Example

TE0725LP Basic Example

TE0725LP Basic Example

TE0725LP Basic Example

TE0714 VIO LED Design

TE0714 Basic Barmetal Example

TE0763 Hello World Example

TE0710 MicroBlaze System