RFSoC Module with AMD Zynq™ UltraScale+™ ZU47DR-1E, 4 GByte DDR4, 6.5 x 9 cm

Price upon request

Article number: TE0835-03-TXE81-A

Article status: Upgrade available

Stock: 0

Product information "RFSoC Module with AMD Zynq™ UltraScale+™ ZU47DR-1E, 4 GByte DDR4, 6.5 x 9 cm"

The predecessor of this article is TE0835-02-TXE21-A. All changes are in the Product Change Notification (PCN).

The Trenz Electronic TE0835 is an extended-grade module based on AMD Zynq™ UltraScale+™ RFSoC. The module is equipped with 4 x 1 GByte DDR4 SDRAM memory, 2 x 64 MByte SPI Flash memory, USB2.0, Ethernet transceiver and 2 x Samtec Razor Beam Board to Board (B2B) connectors. The system controller CPLD is provided by Lattice MachXO2.

The Zynq UltraScale+ RFSoC family integrates key subsystems for multiband, multi-mode cellular radios and cable infrastructure (DOCSIS) into an SoC platform that contains a feature-rich 64-bitquad-core Arm Cortex-A53 and dual-core Arm Cortex-R5 based processing system.

All parts are at least extended temperature range of 0°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Key Features

SoC/FPGA
- Device: AMD Zynq™ UltraScale+™ RFSoC XCZU47DR-1FFVE1156E Gen3
- Other assembly options of this series are available with devices
  - ZU25, ZU27, ZU28 (Gen1)
  - ZU43, ZU48 (Gen3)
- Speedgrade: -1
- Temperature range: Extended
- Package: FFVE1156
- Engine: Quad-core Arm Cortex-A53 MPCore up to 1.3GHz
- 8 x 14-bit RF-ADCs with 5 GSPS
- 8 x 14-bit RF-DACs with 9.85 GSPS

RAM/Storage
- 4 x 1 GByte DDR4 SDRAM
- 2 x 64 MByte SPI Boot Flash (dual parallel)
- 2 Kbit I2C serial EEPROM with EUI-48 Node Identity

On Board
- Lattice MachXO2 CPLD
- Programmable ultra-high-performance DSPLL
- USB2.0 OTG transceiver
- Gigabit Ethernet transceiver
- 3 x Oscillators
- 4 x user LEDs

Interface
- 2 x Samtec Razor Beam ST5 (2 x 80 pol) Board to Board connectors
- Total I/O: 40 IOs, 20 LVDS, 32 MIO
- 8 x GTY
- 4 x GTR

Power
- 5V +/- 10 % Input Supply Voltage

Dimension
- 6,5 x 9 cm

Other assembly options for cost or performance optimization plus high volume prices available on request.

Recommended Software

Vivado Enterprise Edition (paid version)

The Vivado Enterprise Edition is the full-featured version of the design suite and supports all AMD devices.

Overview Vivado Standard and Enterprise Edition

Development Support

Latest documentation, design support files and reference designs with source files are available for download free of charge.

Scope of Delivery

1 x TE0835-03-TXE81-A Trenz Electronic RFSoC module with AMD Zynq™ UltraScale+™ RFSoC ZU47DR

Additional Information

Manufacturer's article number: TE0835-03-TXE81-A
Trenz Electronic TE0835 Wiki
AMD Zynq™ UltraScale+™ RFSoC Product Page
AMD Zynq™ UltraScale+™ RFSoC Product Selection Guide (PDF)
Support Forum

All modules produced by Trenz Electronic are developed and manufactured in Germany.

The online pictures of this product are not a legally binding offer, but are symbol pictures for illustration and presentation only.

Properties "RFSoC Module with AMD Zynq™ UltraScale+™ ZU47DR-1E, 4 GByte DDR4, 6.5 x 9 cm"

Properties

FPGA Manufacturer:	AMD
FPGA/SoC Architecture:	UltraScale+
FPGA/SoC Family:	Zynq
FPGA/SoC Type:	RFSoC
Form Factor:	6.5 × 9 cm

Data according to manufacturer. Errors and changes reserved.

Downloads

File	File-Extension	Description
Bit-File	*.bit	FPGA Configuration File
Diverse Reports	--	Report files in different formats

Component	Description
IP-Interfaces	I2C, ASIO (AXI-Stream to IO), SPI-Flash, Uart

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	I2C,SPI-Flash,UART
TE-IP	ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO
TE-IP	Startupe2,LabTools Frequency Counter

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Xilinx-IP	VIO (Virtual Input/Output)
TE-IP	Labtools Frequency Counter, Startupe2 Primitive Wrapper

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
Reference Design	Reference Designs sort by ISE/EDK Version
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Component	Description
Interface IPs	DDR3, GPIO, Uart0, QSPI and Ethernet

Application	Description
hello_world	Xilinx Hello World Example (.elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	MicroBlaze, MB-Debug, Uartlite, MIG7 for DDR3, QSPI, Timer, Ethernet Lite
TE-IP	ASIO GPIO (AXI-Stream to GPIO)

Application	Description
Hello World	Xilinx Hello world ( generate elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO,ILA
TE-IP	unio_mac

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Interface IPs	QSPI, Uart, ASIO (Axi-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	ILA, VIO, CLK-Wizard
TE-IP	F32C, Vector_LED, UART_MON

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Component	Description
IP-Interfaces	DDR3, QSPI, Uart, I2C, Ethernet, ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite, VIO
TE-IP	ASIO (AXI-Stream to IO), labtools_fmeter

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
te_spi_bootloader	SPI Bootloader (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
memory_tests	Xilinx Memory Example (.elf only)

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Component	Description
Zynq Processor	activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C,2x SD,1x Ethernet

Application	Description
zynq_fsbl	Zynq First Stage Bootloader (for hdmi modified and provided as library in /sw_lib/)
hello_world	Xilinx Hello World Example

Digilent
OHO-Elektronik
Sundance
Trenz_Electronic - Documents and Design files for Trenz Electronic Products
inrevium
reference

TE0835 - 6.5 x 9 cm RFSoC module with Xilinx Zynq UltraScale+ RFSoC

TE0835 - Wiki with TRM, reference projects, application notes and more
- TE0835 TRM - Technical Reference Manual
- TE0835 Reference Designs - Reference Design Description for Vivado 2017.2 and newer
- TE0835 CPLD Firmware - Firmware Description
- TE0835 Product Change Notifications - PCN (see also Schematic Change History and TRM)
6.5 x 9 SoM SS5/ST5 B2B Connectors - overview, compatibility, mating heights and speed rating
TE0835 Getting Started - Basic note to start up Carrier with TE080x modules

Links

Shop TE0835 - contains prices, available stock, disposability, scope of delivery and more
Download area - various reference designs, schematics, hardware designs and more
Pinout/Tracelength Table - illustration of pinout, tracelength and cross reference Information of modules with different baseboards

6.5 x 9 Carrier

6.5 x 9 SoM Carriers- overview of available carrier boards for all 6.5 x 9 cm modules

Support

For support, please go to http://forum.trenz-electronic.de/ or contact support@trenz-electronic.de

Name	Folder	Description
Source Name	<design_name><folder>	Source Description
PetaLinux Project	<design_name>/os/petalinux	PetaLinux Project with Ethernet,USB,RTC

RFSoC Module with AMD Zynq™ UltraScale+™ ZU47DR-1E, 4 GByte DDR4, 6.5 x 9 cm

Product information "RFSoC Module with AMD Zynq™ UltraScale+™ ZU47DR-1E, 4 GByte DDR4, 6.5 x 9 cm"

Key Features

Recommended Software

Development Support

Scope of Delivery

Additional Information

Downloads

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