SoC Module with AMD Zynq™ 7020-2I, 512 MByte DDR3L, 3 x Ethernet

US$397.46

Article number: TE0729-03-62I63MA

Article status: Full production

Stock: 97

Quantity	Unit price
To 9	US$397.46
From 10	US$357.71
From 25	US$337.84
From 50	US$317.97
From 100	US$298.10
From 250	US$278.22
From 500	US$258.35
From 1000	US$238.48

Product information "SoC Module with AMD Zynq™ 7020-2I, 512 MByte DDR3L, 3 x Ethernet"

The predecessor of this article is TE0729-02-62I63MA. All changes are in the Product Change Notification (PCN).

The Trenz Electronic TE0729 is an industrial-grade SoC module integrating a AMD Zynq™ 7020 with a Gigabit Ethernet transceiver, 2 x 100 Mbit Ethernet, 512 MByte DDR3L SDRAM, 32 MByte Flash memory for conﬁguration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of conﬁgurable I/O's is provided via rugged high-speed stacking strips.

All this on a tiny footprint of 5.2 x 7.6 cm at the most competitive price. These high-density integrated modules are smaller than a credit card and available in several variants.

All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Key Features

SoC / FPGA
- Device: AMD Zynq™ XC7Z020-2CLG484I
- Speedgrade: -2
- Temperature range: Industrial
- Package: CLG484I

RAM / Storage
- 512 MByte (16-bit) DDRL3 SDRAM
- 32 MByte QSPI-Flash
- 8 GByte e.MMC Memory
- 3 x 2 Kbit serial EEPROM with EUI-48 Node Identity

On Board
- Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
- System Management
- USB 2.0 High-Speed ULPI transceiver with full OTG support
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- User LED

Interface
- 136 FPGA I/O's (58 LVDS pairs possible) and 6 PS MIO's available on board-to-board connectors
- Plug-on module with two 120-pin connectors
- 1 x 10/100/1000 Mbps Ethernet transceiver PHY
- 2 x 10/100 Mbps Ethernet transceiver PHYs

Power
- Evenly-spread supply pins for good signal integrity
- On-board high-efficiency DC/DC converter
  - 4.0 A x 1.0V power rail
  - 1.5 A x 1.5V power rail
  - 1.5 A x 1.8V power rail
  - 1.5 A x 2.5V power rail

Dimension
- 5.2 x 7.6 cm

Other assembly options for cost or performance optimization plus high volume prices available on request.

Recommended Software

Vivado Standard Edition (free version)

The Vivado Standard Edition is the FREE version of the Vivado design suite. Vivado Standard delivers instant access to some basic Vivado features and functionality at no cost.

Overview Vivado Standard and Enterprise Edition

Development Support

There is a base board available for this module.

Latest documentation, design support files and reference designs with source files are available for download free of charge.

Scope of Delivery

1 x TE0729-03-62I63MA Trenz Electronic SoC module with AMD Zynq™ 7020

Additional Information

Manufacturer's article number: TE0729-03-62I63MA
Trenz Electronic TE0729 Wiki
Support Forum

All modules produced by Trenz Electronic are developed and manufactured in Germany.

The online pictures of this product are not a legally binding offer, but are symbol pictures for illustration and presentation only.

Properties "SoC Module with AMD Zynq™ 7020-2I, 512 MByte DDR3L, 3 x Ethernet"

Properties

FPGA Manufacturer:	AMD
FPGA/SoC Architecture:	7 Series
FPGA/SoC Family:	Zynq
FPGA/SoC Type:	SoC
Form Factor:	5.2 × 7.6 cm

Data according to manufacturer. Errors and changes reserved.

Downloads

File	File-Extension	Description
Bit-File	*.bit	FPGA Configuration File
Diverse Reports	--	Report files in different formats

Component	Description
IP-Interfaces	I2C, ASIO (AXI-Stream to IO), SPI-Flash, Uart

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	I2C,SPI-Flash,UART
TE-IP	ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO
TE-IP	Startupe2,LabTools Frequency Counter

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Xilinx-IP	VIO (Virtual Input/Output)
TE-IP	Labtools Frequency Counter, Startupe2 Primitive Wrapper

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
Reference Design	Reference Designs sort by ISE/EDK Version
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Component	Description
Interface IPs	DDR3, GPIO, Uart0, QSPI and Ethernet

Application	Description
hello_world	Xilinx Hello World Example (.elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	MicroBlaze, MB-Debug, Uartlite, MIG7 for DDR3, QSPI, Timer, Ethernet Lite
TE-IP	ASIO GPIO (AXI-Stream to GPIO)

Application	Description
Hello World	Xilinx Hello world ( generate elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO,ILA
TE-IP	unio_mac

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Interface IPs	QSPI, Uart, ASIO (Axi-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	ILA, VIO, CLK-Wizard
TE-IP	F32C, Vector_LED, UART_MON

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Component	Description
IP-Interfaces	DDR3, QSPI, Uart, I2C, Ethernet, ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite, VIO
TE-IP	ASIO (AXI-Stream to IO), labtools_fmeter

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
te_spi_bootloader	SPI Bootloader (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
memory_tests	Xilinx Memory Example (.elf only)

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Component	Description
Zynq Processor	activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C,2x SD,1x Ethernet

Digilent
OHO-Elektronik
Sundance
Trenz_Electronic - Documents and Design files for Trenz Electronic Products
inrevium
reference

TE0729 - 5.2 x 7.6 cm SoC module with Xilinx Zynq-7020

TE0729 - Wiki with TRM, reference projects, application notes and more
- TE0729 TRM - Technical Reference Manual
- TE0729 CPLD Firmware - Firmware Description
- TE0729 Product Change Notifications - PCN (see also Schematic Change History and TRM)
- TE0729 Reference Designs - Reference Design Description for Vivado 2017.2 and newer
5.2 x 7.6 SoM BTE and BSE B2B Connectors - overview, compatibility, mating heights and speed rating

Links

Shop TE0729 - contains prices, available stock, disposability, scope of delivery and more
Download area - various reference designs, schematics, hardware designs and more
Pinout/Tracelength Table - illustration of pinout, tracelength and cross reference Information of modules with different baseboards

5.2 x 7.6 Carrier

5.2 x 7.6 Carriers - overview of available carrier boards for all 5.2 x 7.6 cm SoM modules

Notes

Watchdog does not work correctly on all modules with Firmware released before 2017.08.22. Please update Firmware on CPLD. For questions, write to Trenz Electronic support.

2 Firmware variants with swapped external reset input and output direction are available. See 71631084 section of this document. Firmware for J2-89 as external reset output and J2-91 as external reset input will be used as default firmware.

Support

For support, please go to http://forum.trenz-electronic.de/ or contact support@trenz-electronic.de

Application	Description
zynq_fsbl	Default Xilinx FSBL
u-boot	Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>)

Application	Description
zynq_fsbl	Zynq First Stage Bootloader (Modified)
hello_world	TE0720 Xilinx Hello World Example
u-boot	Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default)

Name	Folder	Description
Source Name	<design_name><folder>	Source Description
PetaLinux Project	<design_name>/os/petalinux	PetaLinux Project with Ethernet,USB,RTC

SoC Module with AMD Zynq™ 7020-2I, 512 MByte DDR3L, 3 x Ethernet

Product information "SoC Module with AMD Zynq™ 7020-2I, 512 MByte DDR3L, 3 x Ethernet"

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Development Support

Scope of Delivery

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