GigaBee XC6SLX45-2, 2 x 128 MByte SDRAM, industrial temperature range

US$177.31

Article number: TE0600-03I

Article status: Upgrade available

Stock: 0

Product information "GigaBee XC6SLX45-2, 2 x 128 MByte SDRAM, industrial temperature range"

This product is offered at a discount because there is already a successor.
Only valid while stocks last!
____________________________________________________

The predecessor of this article is TE0600-02I. All changes are in the Product Change Notification (PCN).

The successor of this article is TE0600-03-52I11-A. All changes are in the Product Change Notification (PCN).

The Trenz Electronic TE0600-03I GigaBee XC6SLX is an industrial FPGA micromodule integrating a AMD/Xilinx Spartan-6 LX FPGA, Gigabit Ethernet transceiver (physical layer), two independent banks of 16-bit-wide 128 MBytes DDR3 SDRAM (optional 2 x 512 MByte DDR3 SDRAM in 2 banks), 16 MBytes SPI Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.

All this on a tiny footprint, smaller than a credit card, at the most competitive price. Modules in 4 x 5 cm form factor are fully mechanically and largely electrically compatible among each other.

All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Sample Applications

Cryptographic hardware module
Digital signal processing
Embedded educational platform
Embedded industrial OEM platform
Embedded system design
Emulation platforms
FPGA graphics
Image processing
IP (intellectual property) cores
Low-power design
Parallel processing
Rapid prototyping
Reconfigurable computing
System-on-Chip (SoC) development

Key Features

AMD/Xilinx Spartan-6 LX FPGA, depending on model: LX45, LX100 or LX150
FPGA Design Security Solution
10/100/1000 tri-speed Gbit Ethernet transceiver (PHY)
2 independent 16-bit-wide 1 Gbit (128 MByte) DDR3 SDRAM
(optional: 2 independent 4 Gbit (512 MByte) DDR3 SDRAM in 2 banks)
128 Mbit (16 MByte) SPI Flash memory (for configuration and operation)
JTAG port (SPI indirect)
FPGA configuration through:
- B2B connector
- JTAG port
- SPI Flash memory
Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
Up to 52 differential, up to 109 single-ended (+ 1 dual-purpose) FPGA I/O pins available on B2B strips
High-efficiency DC-DC switching regulators
125 MHz reference clock signal
Single-ended custom oscillator (option)
eFUSE bit-stream encryption (LX100 or larger)
1 user LED
Evenly-spread supply pins for good signal integrity

Specifications

AMD/Xilinx Spartan-6 XC6SLX45-2FGG484I FPGA
10/100/1000 Gbit Ethernet transceiver (physical layer) Marvell Semiconductor 88E1111
128 Mbit (16 MByte) serial Flash memory with dual/quad SPI interface
48-bit node address chip Maxim Integrated Products DS2502-E48 (contains valid MAC adress)
2 x fine-pitch (0.5 mm) 100-pin high-speed (up to 10.0 GHz / 20 Gbps) hermaphroditic strips LSHM-150-04.0-L-DV-A-S-K-TR
Up to 52 differential FPGA input/output pins available on B2B strips
Up to 109 single-ended (+ 1 dual-purpose) FPGA input/output pins available on B2B strips
Ethernet (PHY), JTAG and SPI pins available on B2B strips
4.0 A high-efficiency DC-DC switching regulator for power rail 1.2V
1.5 A high-efficiency DC-DC switching regulator for power rail 1.5V
2 x 800 mA DC-DC linear regulator for power rails 2.5V and VCCAUX
Processor supervisory circuits with power-fail and watchdog Texas Instruments TPS3705-33
125 MHz clock signal (system + user)
Footprint for custom single-ended oscillator (option)
Power supply voltage: 3.3V
Dimensions: 50 mm × 40 mm (20 cm²)
Stacking hight: 8 mm
Maximum height on carrier board surface: 12 mm (standard connectors)
Weight: 17.2 ± 0.1 g

Other assembly options for cost or performance optimization plus high volume prices available on request.

Recommended Software

for Trenz Electronic modules with Spartan-3A, -3E and Spartan-6 LX45/LX75

ISE Design Suite: WebPACK Edition

ISE WebPACK delivers a complete, front-to-back design flow providing instant access to the ISE features and functionality at no cost.

https://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html

Development Support

There is a base board available for this module.

Latest documentation, design support files and reference designs with source files are available for download free of charge.

Scope of Delivery

1 x TE0600-03I Trenz Electronic GigaBee module with AMD/Xilinx Spartan-6 FPGA
8 x screws
4 x bolts

Additional Information

Manufacturer's article number: TE0600-03I
Trenz Electronic TE0600 Wiki
Support Forum

All modules produced by Trenz Electronic are developed and manufactured in Germany.

Downloads

File	File-Extension	Description
Bit-File	*.bit	FPGA Configuration File
Diverse Reports	--	Report files in different formats

Component	Description
IP-Interfaces	I2C, ASIO (AXI-Stream to IO), SPI-Flash, Uart

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	I2C,SPI-Flash,UART
TE-IP	ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO
TE-IP	Startupe2,LabTools Frequency Counter

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Xilinx-IP	VIO (Virtual Input/Output)
TE-IP	Labtools Frequency Counter, Startupe2 Primitive Wrapper

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
Reference Design	Reference Designs sort by ISE/EDK Version
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Component	Description
Interface IPs	DDR3, GPIO, Uart0, QSPI and Ethernet

Application	Description
hello_world	Xilinx Hello World Example (.elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	MicroBlaze, MB-Debug, Uartlite, MIG7 for DDR3, QSPI, Timer, Ethernet Lite
TE-IP	ASIO GPIO (AXI-Stream to GPIO)

Application	Description
Hello World	Xilinx Hello world ( generate elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO,ILA
TE-IP	unio_mac

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Interface IPs	QSPI, Uart, ASIO (Axi-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	ILA, VIO, CLK-Wizard
TE-IP	F32C, Vector_LED, UART_MON

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Component	Description
IP-Interfaces	DDR3, QSPI, Uart, I2C, Ethernet, ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite, VIO
TE-IP	ASIO (AXI-Stream to IO), labtools_fmeter

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
te_spi_bootloader	SPI Bootloader (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
memory_tests	Xilinx Memory Example (.elf only)

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Component	Description
Zynq Processor	activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C,2x SD,1x Ethernet

Application	Description
zynq_fsbl	Zynq First Stage Bootloader (for hdmi modified and provided as library in /sw_lib/)
hello_world	Xilinx Hello World Example

File	File-Extension	Description
Bin-File	*.bin	Flash Configuration File with Boot-Image for Zynq-FPGAs
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlace Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
BIF-File	*.bif	File with description to generate Bin-File
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Diverse Reports	--	Report files in different formats

Digilent
OHO-Elektronik
Sundance
Trenz_Electronic - Documents and Design files for Trenz Electronic Products
inrevium
reference

TE0600 GigaBee 4 x 5 cm FPGA module with Xilinx Spartan-6 LX

TE0600 - Wiki with TRM, reference projects, application notes and more
- TE0600 TRM - Technical Reference Manual
- TE0600 Product Change Notifications - PCN (see also Schematic Change History and TRM)
4 x 5 SoM LSHM B2B Connectors - overview, compatibility, mating heights and speed rating
4 x 5 SoMs Handling and Usage Precautions - general handling and removal instructions

4 x 5 Carrier

4 x 5 SoM Carriers - overview of available carrier boards for all 4 x 5 cm modules

Support

For support, please go to http://forum.trenz-electronic.de/ or contact support@trenz-electronic.de

Accessories

XUP USB-JTAG programming cable

The XUP-USB programming cable is compatible with Xilinx's Platform Cable USB.

Article number: 23260

Stock: 1

US$102.76

Details

XUP USB-JTAG Programming Cable - academic

The XUP-USB programming cable is compatible with Xilinx's Platform Cable USB.

Article number: 23272

Stock: 0

US$139.07

Details

Samtec Razor Beam REF-189016-02, LF-04.0, 100 pins, for all 4 x 5 SoMs

Board-to-Board Connector for all 4 x 5 SoMs (JB1/JB2, JM1/JM2), lead style -04.0

Article number: 23838

Stock: 0

From US$3.87

Details

JTAG HS2 Programming Cable

The Joint Test Action Group (JTAG)-HS2 programming cable is a high-speed programming solution for Xilinx field-programmable gate arrays (FPGAs). The cable is fully compatible will all Xilinx tools and can be seamlessly driven from iMPACT, Chipscope, an

Article number: 24624

Stock: 0

US$54.02

Details

Heat Sink for Trenz Electronic Modules TE0600, spring-loaded embedded

Please check assembly instructions! Made especially for modules from the TE0600 series revision 03/04

Article number: 26920

Stock: 23

From US$20.71

Details

GigaBee XC6SLX carrier board

B2B pins routed to standard 2.54 mm headers; MicroSD card slot; one 2x6 Digilent Pmod socket;

Article number: TE0603-03

Stock: 0

US$76.16

Details

Name	Folder	Description
Source Name	<design_name><folder>	Source Description
PetaLinux Project	<design_name>/os/petalinux	PetaLinux Project with Ethernet,USB,RTC

GigaBee XC6SLX45-2, 2 x 128 MByte SDRAM, industrial temperature range

Product information "GigaBee XC6SLX45-2, 2 x 128 MByte SDRAM, industrial temperature range"

Sample Applications

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Specifications

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Scope of Delivery

Additional Information

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