UltraSOM+ MPSoC Module with AMD Zynq™ UltraScale+™ ZU9EG-1E, 4 GByte DDR4, LP

US$1,013.88

Possible to order, delivery time on request.

Article number: TE0808-05-9BE21-F

Article status: Upgrade available

Stock: 0

Product information "UltraSOM+ MPSoC Module with AMD Zynq™ UltraScale+™ ZU9EG-1E, 4 GByte DDR4, LP"

The predecessor of this article is TE0808-05-9BE21-L. All changes are in the Product Change Notification (PCN).

This module is identical to variant TE0808-05-9BE21-A except the lower 1 mm Samtec connectors.

Note: Due to the new revision the height profile of the module has changed.
Using TE0808-05 board as a replacement or in system(s) designed for TE0808-04, a review and adaption of mechanics e.g. cooling solutions must be implemented.
-------------------------

This module will not be discontinued, but we recommend the TE0818 module series with an improved connector for new projects.
-------------------------
The Trenz Electronic TE0808-05-9BE21-F is a MPSoC module integrating a AMD Zynq™ UltraScale+™ ZU9EG, 4 GByte DDR4 SDRAM and 128 MByte Flash memory for configuration and operation, 20 x serial high speed transceivers, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.

All this on a tiny footprint of 5.2 x 7.6 cm at the most competitive price. These high-density integrated modules are smaller than a credit card and available in several variants.

All parts are at least extended temperature range of 0°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Key Features

AMD Zynq™ UltraScale+™ XCZU9EG-1FFVC900E
ZU9EG 900 Pin Packages
3 mm mounting holes for skyline heat spreader
Size: 52 x 76 mm
B2B Connectors: 4 x 160 pin
Rugged for shock and high vibration
4 GByte DDR4 SDRAM, 64-Bit width
128 MByte SPI Boot Flash (dual parallel)
User I/Os
- 65 x PS MIOs, 48 x PL HD GPIOs, 156 x PL HP GIPIOs (3 banks)
- Serial transceivers: 4 x PS-GTR, 16 x PL-GTH
- Transceiver clocks inputs and outputs
- PLL clock generator inputs and outputs
Si5345 - 10 output PLL
All power supplies on board, single 3.3V Power required
- 14 on-board DC/DC regulators and 13 LDOs
- LP, FP, PL separately controlled power domains
Support for all boot modes (except NAND) and scenarios
Support for any combination of PS connected peripherals
Evenly spread supply pins for good signal integrity

Other assembly options for cost or performance optimization plus high volume prices available on request.

Recommended Software

Vivado Enterprise Edition (paid version)

The Vivado Enterprise Edition is the full-featured version of the design suite and supports all AMD devices.

Overview Vivado Standard and Enterprise Edition

Development Support

There is a base board available for this module.

Latest documentation, design support files and reference designs with source files are available for download free of charge.

Scope of Delivery

1 x TE0808-05-9BE21-F Trenz Electronic MPSoC module with AMD Zynq™ UltraScale+™ ZU9EG, low profile

Additional Information

Manufacturer's article number: TE0808-05-9BE21-F
Trenz Electronic TE0808 Wiki
Support Forum

All modules produced by Trenz Electronic are developed and manufactured in Germany.

Properties "UltraSOM+ MPSoC Module with AMD Zynq™ UltraScale+™ ZU9EG-1E, 4 GByte DDR4, LP"

Properties

FPGA Manufacturer:	AMD
FPGA/SoC Architecture:	UltraScale+
FPGA/SoC Family:	Zynq
FPGA/SoC Type:	MPSoC
Form Factor:	5.2 × 7.6 cm

Data according to manufacturer. Errors and changes reserved.

Downloads

File	File-Extension	Description
Bit-File	*.bit	FPGA Configuration File
Diverse Reports	--	Report files in different formats

Component	Description
IP-Interfaces	I2C, ASIO (AXI-Stream to IO), SPI-Flash, Uart

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	I2C,SPI-Flash,UART
TE-IP	ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO
TE-IP	Startupe2,LabTools Frequency Counter

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Xilinx-IP	VIO (Virtual Input/Output)
TE-IP	Labtools Frequency Counter, Startupe2 Primitive Wrapper

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
Reference Design	Reference Designs sort by ISE/EDK Version
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Component	Description
Interface IPs	DDR3, GPIO, Uart0, QSPI and Ethernet

Application	Description
hello_world	Xilinx Hello World Example (.elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	MicroBlaze, MB-Debug, Uartlite, MIG7 for DDR3, QSPI, Timer, Ethernet Lite
TE-IP	ASIO GPIO (AXI-Stream to GPIO)

Application	Description
Hello World	Xilinx Hello world ( generate elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO,ILA
TE-IP	unio_mac

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Interface IPs	QSPI, Uart, ASIO (Axi-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	ILA, VIO, CLK-Wizard
TE-IP	F32C, Vector_LED, UART_MON

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Component	Description
IP-Interfaces	DDR3, QSPI, Uart, I2C, Ethernet, ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite, VIO
TE-IP	ASIO (AXI-Stream to IO), labtools_fmeter

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
te_spi_bootloader	SPI Bootloader (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
memory_tests	Xilinx Memory Example (.elf only)

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Component	Description
Zynq Processor	activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C,2x SD,1x Ethernet

Application	Description
zynq_fsbl	Zynq First Stage Bootloader (for hdmi modified and provided as library in /sw_lib/)
hello_world	Xilinx Hello World Example

Digilent
OHO-Elektronik
Sundance
Trenz_Electronic - Documents and Design files for Trenz Electronic Products
inrevium
reference
Files SBSE____.ZZC
Size 4 B / Modified 29.09.2026 - 16:31:35

TE0808 - 5.2 x 7.6 cm MPSoC module with Xilinx Zynq UltraScale+

TE0808 - UltraSoM+ - Wiki with TRM, reference projects, application notes and more
- TE0808 TRM - Technical Reference Manual
- TE0808 Reference Designs - Reference Design Description for Vivado 2017.2 and newer
- TE0808 Product Change Notifications - PCN (see also Schematic Change History and TRM)
5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors - overview, compatibility, mating heights and speed rating
5.2 x 7.6 UltraSoM+ Integration Guide - module and carrier board power connection, PCB Design notes and more
TEBF0808 Getting Started - Basic note to start up Carrier with TE080x modules

Links

Shop TE0808 - contains prices, available stock, disposability, scope of delivery and more
Download area - various reference designs, schematics, hardware designs and more
Pinout/Tracelength Table - illustration of pinout, tracelength and cross reference Information of modules with different baseboards

5.2 x 7.6 Carrier

5.2 x 7.6 Carriers - overview of available carrier boards for all 5.2 x 7.6 cm UltraSoM+ modules

Starter Kit

Starter Kit 808 - module with carrier, enclosure and more

3rd Party Links

Design Time and Run Time Resources for Zynq Ultrascale+ TE0808-04-15EG-1EE with SDSoC 2018.2 Support - provided by UTIA
FitOptiVis From the cloud to the edge - smart IntegraTion and OPtimization Technologies for highly efficient Image and VIdeo processing Systems - provided by UTIA
Arrowhead Tools Arrowhead Tools for Engineering of Digitalisation Solutions - provided by UTIA
Testing all Samples from Xilinx Vitis AI Library 2.0 on Trenz Electronic board TE0808 SoM + TEBF0808 Carrier - provided by UTIA
All VART Examples from Xilinx Vitis AI 2.0 for Trenz Electronic board TE0808 SoM + TEBF0808 Carrier - provided by UTIA
Xilinx Vitis AI 'facedetect' Demo on Trenz Electronic board TE0808 SoM + TEBF0808 Carrier - provided by UTIA

Support

For support, please go to http://forum.trenz-electronic.de/ or contact support@trenz-electronic.de

Name	Folder	Description
Source Name	<design_name><folder>	Source Description
PetaLinux Project	<design_name>/os/petalinux	PetaLinux Project with Ethernet,USB,RTC

UltraSOM+ MPSoC Module with AMD Zynq™ UltraScale+™ ZU9EG-1E, 4 GByte DDR4, LP

Product information "UltraSOM+ MPSoC Module with AMD Zynq™ UltraScale+™ ZU9EG-1E, 4 GByte DDR4, LP"

Key Features

Recommended Software

Development Support

Scope of Delivery

Additional Information

Downloads

TEC0850 Basic Design

CR00100 Basic Example

CR00100 Basic Example

CR00103 Hyperram Citrobits

CR00103 Certus Test

CR00107 Basic Hello World Example

TE0802 Basic Linux Example

TE0802 Basic Linux Example

TE0802 Basic Linux Example

TE0802 Basic Linux Example

TE0950 Vitis AI Reference Design

TE0950 Basic Linux Example

TE0950 Basic Linux Example

TEI0022 Basic Example

TEI0022 Basic Example

TE0717 Hello World Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0003 LED Sequencer Example

TEI0003 NIOS SDRAM Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0010 Basic Example

TEI0010 Basic Example

TEI0010 Basic Example

TEI0010 Basic Example

TEM0001 Test Board Example

TEI0050 Basic Example

TEI0050 Basic Example

TEI0050 Basic Example

TEI0015 DAQ Capture Demo

TEI0015 Data Capture Demo

TEI0015 Jupyter Demo

TEI0016 DAQ Capture Demo

TEI0016 Data Capture Demo

TEI0016 Jupyter Demo

TEI0023 DAQ Capture Demo

TEI0023 Data Capture Demo

TEI0023 Jupyter Demo

TE0890 Hello World Example

TE0890 Hello World Example

ZynqberryZero Demo VIDEO/AUDIO Design with RPI video camera stream to monitor

Basic Linux Example

ZynqberryZero Demo VIDEO/AUDIO Design with RPI video camera stream to monitor

ZynqberryZero Demo VIDEO/AUDIO Design with RPI video camera stream to monitor

TEM0005 Webserver Demo1

MicroBlaze Basic-System

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 Basic Example

TE0725LP Frequency Measurement

TE0725LP Basic Example

TE0725LP Basic Example

TE0725LP Basic Example

TE0725LP Basic Example

TE0725LP Basic Example

TE0714 VIO LED Design

TE0714 Basic Barmetal Example

TE0763 Hello World Example